The present disclosure relates to solid-state image sensors and cameras, and more particularly to solid-state image sensors having a pixel addition function, and cameras.
Charge coupled devices (CCDs) for digital still cameras typically have ten millions or more of pixels. The number of pixels in the horizontal direction has reached about 4,000, and horizontal transfer electrodes forming a horizontal transfer section have been reduced in size. Thus, in conventional two-phase drive in which one transfer packet of the horizontal transfer section corresponds to one column in a vertical transfer section, capacitance between electrodes is significantly increased, resulting in high power consumption.
In order to solve this problem, a method has been proposed in which signal charges of one line are divided for interlace output. For example, the number of transfer packets in the horizontal transfer section is one third of the number of columns in the vertical transfer section, and an operation of transferring signal charges from the vertical transfer section to the horizontal transfer section and transferring the signal charges from the horizontal transfer section to an output section is divided into three operations. This can reduce the number of electrodes that form the horizontal transfer section, thereby reducing the capacitance between the electrodes. Thus, power consumption can be reduced. In the solid-state image sensors having such a structure, the number of transfer packets in the horizontal transfer section is less than the number of columns in the vertical transfer section. Thus, a transfer control section is required which selectively controls signal charge transfer from the vertical transfer section to the horizontal transfer section. The transfer control section needs to have a function to hold the signal charges during the first transfer operation.
The CCDs have been required to have not only an imaging mode (hereinafter referred to as the normal mode) in which signals of light-receiving elements are read from all the pixels and used as a still picture, but also a movie mode in which a moving picture is displayed on a liquid crystal monitor or is recorded. Although the frame rate can be 2-3 frames per second in the normal mode, the frame rate needs to be 30 frames per second in the movie mode. Thus, in the movie mode, the signal charges that are obtained from a plurality of pixels are added together within the image sensor, or the signal charges that are read from the pixels are selectively skipped, thereby reducing the number of output signals, and implementing a high frame-rate moving picture. In the case where the number of pixels in the normal mode is ten millions, an image needs to be compressed to about 1/10 of a still image even in a high-resolution 720-p output (1,280 by 720 pixels), whereby the number of signal charges to be added together is increased.
Solid-state image sensors for digital still cameras typically use a Bayer pattern, and add signal charges of adjoining pixels of the same color together. Such addition of signal charges in the solid-state image sensors requires addition in the vertical direction and addition in the horizontal direction. The addition of signal charges in the vertical direction can be performed within the vertical transfer section by providing a plurality of vertical transfer electrodes configured to perform a read operation from photoelectric conversion elements to the vertical transfer section, and driving the vertical transfer electrodes at appropriate timings. However, in order to perform the addition of signal charges in the horizontal direction, a transfer control section that selectively controls signal charge transfer needs to be provided between the vertical transfer section and the horizontal transfer section.
The following example is known as a solid-state image sensor provided with such a transfer control section (see, e.g., Japanese Patent Publication No. 2006-310655). As shown in FIG. 25, charge transfer sections (vertical output gate (VOG) sections) 504 are provided between vertical transfer sections 501 and a horizontal transfer section 502. Every two or more adjoining ones of the vertical transfer sections 501 form a group, and each group corresponds to a unit transfer bit of the horizontal transfer section 502. The VOG section 504 is provided for each group, and transfers signal charges from the vertical transfer sections 501 in the group to a corresponding one of the unit transfer bits of the horizontal transfer section 502. Charge holding sections 507 each having a storage section 505 and a holding section 506 are respectively formed between columns “a” and “b” of the vertical transfer sections 501 in the same group and a corresponding one of the VOG sections 504.
Operation of the solid-state image sensor configured as described above will be described below. In this example, the transfer control section described above is a region including the charge holding sections 507 and the VOG sections 504. The horizontal transfer section 502 is described below as three-phase drive. In the normal mode, signal charges of column “c” are transferred to H1 of the horizontal transfer section 502 via the VOG section 504, and are then horizontally transferred to an output section. At this time, signal charges of columns “a” and “b” are held in the charge holding sections 507. After the signal charges of column “c” are transferred, the signal charges of column “a” are transferred to H1 of the horizontal transfer section 502, and are then horizontally transferred to the output section. Thereafter, the signal charges of column “b” are transferred to H1 of the horizontal transfer section 502, and are then horizontally transferred to the output section. Thus, in the normal mode, signal charges of one horizontal line are divided into three parts for output.
On the other hand, in a horizontal three-pixel addition mode, the signal charges of column “a” and the signal charges of column “c” are transferred to H1 of the horizontal transfer section 502 via the VOG section 504. Then, the signal charges are transferred leftward by one unit transfer bit. Thereafter, the signal charges of column “b” are transferred to H1 of the horizontal transfer section 502 via the VOG section 504. The three-pixel addition in the horizontal direction can be performed in this manner. In this operation mode, since the number of signal charges after the addition matches the number of transfer packets in the horizontal transfer section, signal charges of one line need not be divided into three parts for transfer as in the normal mode. In either case, the signal charges are transferred from the vertical transfer sections 501 to the horizontal transfer section 502 via the VOG section 504, and the horizontal transfer sections 501 are coupled to the VOG section 504.